UC3875 PDF

This family of circuits may be configured to provide control in either voltage or current mode operation, with a separate over-current shutdown for fast fault protection. A programmable time delay is provided to insert a dead-time at the turn-on of each output stage. This delay, providing time to allow the resonant switching action, is independently controllable for each output pair A-B, C-D. With the oscillator capable of operation at frequencies in excess of 2MHz, overall switching frequencies to 1MHz are practical.

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This family of circuits may be configured to provide control in either voltage or current mode operation, with a separate over-current shutdown for fast fault protection.

A programmable time delay is provided to insert a dead-time at the turn-on of each output stage. This delay, providing time to allow the resonant switching action, is independently controllable for each output pair A-B, C-D. With the oscillator capable of operation at frequencies in excess of 2MHz, overall switching frequencies to 1MHz are practical. In addition to the standard free running mode, with the CLOCKSYNC pin, the user may configure these devices to accept an external clock synchronization signal, or may lock together up to 5 units with the operational frequency determined by the fastest device.

Protective features include an undervoltage lockout which maintains all outputs in an active-low state until the supply reaches a Over-current protection is provided, and will latch the outputs in the OFF state within 70nsec of a fault.

The current-fault circuitry implements full-cycle restart operation. Additional features include an error amplifier with bandwidth in excess of 7MHz, a 5V reference, provisions for soft-starting, and flexible ramp generation and slope compensation circuitry. All voltages are with respect to ground. Currents are positive into, negative out of, device terminals. Consult Unitrode databook for information regarding thermal specifications and limitations of packages.

Note 5: Delay time can be programmed via resistors from the delay set pins to ground. As an input, this pin provides a synchronization point. In its simplest usage, multiple devices, each with their own local oscillator frequency, may be connected together by the CLOCKSYNC pin and will synchronize on the fastest oscillator.

This pin may also be used to synchronize the device to an external clock, provided the external signal is of higher frequency than the local oscillator. A resistor load may be needed on this pin to minimize the clock pulse width. Since the error amplifier has a relatively low current drive capability, the output may be overridden by driving with a sufficiently low impedance source.

When the voltage at this pin exceeds 2. If a constant voltage above 2. This delay is introduced between turn-off of one switch and turn-on of another in the same leg of the bridge to provide a dead time in which the resonant switching of the external power switches takes place. Separate delays are provided for the two half-bridges to accommodate differences in the resonant capacitor charging currents. EA— error amplifier inverting input : This is normally connected to the voltage divider resistors which sense the power supply output voltage level.

The A-B pair is intended to drive one half-bridge in the external power stage and is syncronized with the clock waveform. The C-D pair will drive the other half-bridge with switching phase shifted with respect to the A-B outputs. Any required bulk reservoir capacitor should parallel this one. Power ground and signal ground may be joined at a single point to optimize noise rejection and minimize DC drops.

Connect a capacitor from here to GND. Because of the 1. Connecting this resistor to the DC input line voltage will provide voltage feed-forward.

VC output switch supply voltage : This pin supplies power to the output drivers and their associated bias circuitry. Connect VC to a stable source above 3V for normal operation, above 12V for best performance. VIN primary chip supply voltage : This pin supplies power to the logic and analog circuitry on the integrated circuit that is not directly associated with driving the output stages.

Connect VIN to a stable source above 12V for normal operation. To ensure proper chip functionality, these devices will be inactive until VIN exceeds the upper undervoltage lockout threshold. This output is capable of delivering about 60mA to peripheral circuitry and is internally short circuit current limited. For best results bypass VREF with a 0. All else remains in the shut-down mode until the output of the reference, VREF, exceeds 4. This arrangement allows the synchronizing connection between ICs to be broken without any local loss of functionality.

Synchronizing the device to an external clock signal may be accomplished with a minimum of external circuitry, as shown in the previous figure. These resistors are shown in the oscillator schematics as R1, RN. This circuit is operable when the chip supply is zero. Q6 is also turned on and held low with a signal from the fault logic portion of the chip. The time is defined by the current sources, I1, which is programmed by an external resistor, RTD.

The voltage on the Delay Set pins is internally regulated to 2. NOTE: There is no way to disable the delay circuitry, and the delay time must be programmed. Clamping the phase shift command to zero. Complete turn-off is ordered for an over-current fault or a low supply voltage. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability.

Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used.

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